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| SMD99C 5-TAP, HCMOS-INTERFACED FIXED DELAY LINE (SERIES SMD99C) FEATURES * * * * * Five equally spaced outputs Designed for surface mounting Low profile (0.175 maximum height) Input & outputs fully CMOS interfaced & buffered 10 T2L fan-out capability IN T2 T4 GND 1 4 10 6 7 8 14 12 data 3 (R) delay devices, inc. PACKAGES IN 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC N/C T1 N/C T3 N/C T5 VDD T1 T3 T5 N/C N/C T2 N/C T4 GND Commercial SMD99C-xx Military SMD99C-xxMC2 FUNCTIONAL DESCRIPTION The SMD99C-series device is a 5-tap digitally buffered delay line. The signal input (IN) is reproduced at the outputs (T1-T5), shifted in time by an amount determined by the device dash number (See Table). The total delay of the line is measured from IN to T5. The nominal tap-to-tap delay increment is given by one-fifth of the total delay. PIN DESCRIPTIONS IN T1-T5 VDD GND Signal Input Tap Outputs +5 Volts Ground SERIES SPECIFICATIONS * * * * * * Minimum input pulse width: 40% of total delay Output rise time: 8ns typical Supply voltage: 5VDC 5% Supply current: ICCL = 40a typical ICCH = 10ma typical Operating temperature: 0 to 70 C Temp. coefficient of total delay: 300 PPM/C DASH NUMBER SPECIFICATIONS Part Number SMD99C-5050 SMD99C-5060 SMD99C-5075 SMD99C-5100 SMD99C-5125 SMD99C-5150 SMD99C-5175 SMD99C-5200 SMD99C-5250 Total Delay (ns) 50 2.5 60 3.0 75 4.0 100 5.0 125 6.5 150 7.5 175 8.0 200 10.0 250 12.5 Delay Per Tap (ns) 10.0 3.0 12.0 3.0 15.0 3.0 20.0 3.0 25.0 3.0 30.0 3.0 35.0 4.0 40.0 4.0 50.0 5.0 NOTE: Any dash number between 5004 and 5250 not shown is also available. 20% 20% 20% 20% 20% VDD IN T1 T2 T3 T4 T5 GND DDU8C Functional diagram (c)1997 Data Delay Devices Doc #97018 1/30/97 DATA DELAY DEVICES, INC. 3 Mt. Prospect Ave. Clifton, NJ 07013 1 SMD99C APPLICATION NOTES HIGH FREQUENCY RESPONSE The SMD99C tolerances are guaranteed for input pulse widths and periods greater than those specified in the test conditions. Although the device will function properly for pulse widths as small as 40% of the total delay and periods as small as 80% of the total delay (for a symmetric input), the delays may deviate from their values at low frequency. However, for a given input condition, the deviation will be repeatable from pulse to pulse. Contact technical support at Data Delay Devices if your application requires device testing at a specific input condition. POWER SUPPLY BYPASSING The SMD99C relies on a stable power supply to produce repeatable delays within the stated tolerances. A 0.1uf capacitor from VDD to GND, located as close as possible to the VDD pin, is recommended. A wide VDD trace and a clean ground plane should be used. DEVICE SPECIFICATIONS TABLE 1: ABSOLUTE MAXIMUM RATINGS PARAMETER DC Supply Voltage Input Pin Voltage Storage Temperature Lead Temperature SYMBOL VDD VIN TSTRG TLEAD MIN -0.3 -0.3 -55 MAX 7.0 VDD+0.3 150 300 UNITS V V C C NOTES 10 sec TABLE 2: DC ELECTRICAL CHARACTERISTICS (0C to 70C, 4.75V to 5.25V) PARAMETER High Level Output Voltage Low Level Output Voltage High Level Output Current Low Level Output Current High Level Input Voltage Low Level Input Voltage Input Current SYMBOL VOH VOL IOH IOL VIH VIL IIH MIN 3.98 TYP 4.4 0.15 MAX UNITS V V mA mA V V A NOTES VDD = 5.0, IOH = MAX VIH = MIN, VIL = MAX VDD = 5.0, IOL = MAX VIH = MIN, VIL = MAX 0.26 -4.0 4.0 3.15 1.35 0.10 VDD = 5.0 Doc #97018 1/30/97 DATA DELAY DEVICES, INC. Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com 2 SMD99C PACKAGE DIMENSIONS .020 .150 C L 1 4 14 12 10 .150 .050 .150 .100 .510 MAX. 6 7 8 .350 TYP. .480 MAX. .510 MAX. .175 MAX. .015 .050 MIN. .001 MIN. SMD99C-xx (Commercial) .020 TYP. 14 13 12 11 10 9 8 .040 TYP. .010.002 .710 .590 .005 MAX. .882 .005 .007 .005 1 2 3 4 5 6 7 .090 .100 .600 .780.020 .280 MAX. .050 .010 SMD99C-xxMC2 (Military) Doc #97018 1/30/97 DATA DELAY DEVICES, INC. 3 Mt. Prospect Ave. Clifton, NJ 07013 3 SMD99C DELAY LINE AUTOMATED TESTING TEST CONDITIONS INPUT: Ambient Temperature: 25oC 3oC Supply Voltage (VDD): 5.0V 0.1V Input Pulse: High = 5.0V 0.1V Low = 0.0V 0.1V Source Impedance: 50 Max. Rise/Fall Time: 5.0 ns Max. (measured between 0.5V and 4.5V ) Pulse Width: PWIN = 1.5 x Total Delay Period: PERIN = 10 x Total Delay OUTPUT: Load: Cload: Threshold: 1 FAST-TTL Gate 5pf 10% 2.5V (Rising & Falling) NOTE: The above conditions are for test only and do not in any way restrict the operation of the device. COMPUTER SYSTEM PRINTER REF PULSE GENERATOR OUT TRIG IN DEVICE UNDER TEST (DUT) T1 T2 T3 T4 T5 IN TRIG TIME INTERVAL COUNTER Test Setup PERIN PWIN TRISE INPUT SIGNAL 4.5V 2.5V 0.5V TFALL VIH 4.5V 2.5V 0.5V VIL TFALL TRISE OUTPUT SIGNAL VOH 2.5V 2.5V VOL Timing Diagram For Testing Doc #97018 1/30/97 DATA DELAY DEVICES, INC. Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com 4 |
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